1. Field of the Invention
The invention relates to optical storage systems, and more particularly, to a clock generator and clock generating method of optical storage systems.
2. Description of the Prior Art
A phase lock loop (PLL) is an essential component of an optical disk drive, for generating needed clock signals for the operation of the optical disk drive. In this way, the optical disk drive can sample the stored data on the optical disk according to the clock signal generated by the PLL. Please refer to FIG. 1, which is a diagram of a typical PLL 100. The PLL 100 comprises a phase detector (PD) 110, a frequency detector (FD) 112, a charge pump 114, a loop filter 116, and a voltage-controlled oscillator (VCO) 118. The functions and operations of the charge pump 114, the loop filter 116, and the VCO 18 are well known and details are thus omitted herein. Because the frequency of the signal read by the optical disk drive from the optical disk varies (for example, the linear velocity of the inner groove is different from that of the outer groove), the PLL 100 first activates the FD 112 to force the frequency of an output clock signal CLK to approach and become roughly equal to the frequency of an input signal Sin. Then, the PLL 100 utilizes the PD 110 to tune the clock signal CLK so that the phase and the frequency of the clock signal can accurately lock on the phase and the frequency of the input signal Sin. This makes the PLL 100 more efficient than a PLL utilizing only a PD to lock on the input signal Sin.
Generally speaking, the FD 112 detects whether the frequency of the clock signal CLK approaches the desired frequency according to a sampling result of a longest signal pulse of the input signal Sin, for example, of an Eight-to-Fourteen Modulation (EFM) signal from an optical disk. If the sampling result of the longest pulse appears longer than a nominal longest length (in the case of DVD, 14T, where T represents the period of the clock signal), then it is determined that the frequency of the clock signal CLK is too high, and the FD 112 should control the VCO 18 to reduce the frequency of the clock signal CLK. If the sampling results of the longest pulses within a certain period of time fail to exceed the nominal longest length, then it is determined that the frequency of the clock signal CLK is too low, and the FD 112 controls the VCO 18 to raise the frequency of the clock signal CLK. Therefore, after a period of time, the frequency of the clock signal CLK controlled by the FD 112 will resemble to a certain degree the desired frequency, and then the PLL 100 will switch to the PD 110 to accurately control the VCO 18 and to lock on the desired clock signal CLK.
However, according to the aforementioned, there still exists a problem. Please refer to FIG. 2, which is a diagram of an EFM signal of a DVD system. As shown in FIG. 2, the sections labeled “A” indicate the above-mentioned longest signal pulse, which is a nominal 14T synchronization pattern in this illustration, where T is the sampling period. As a result, the resolution of frequency estimation is 1/14, or, in other words, the error possibly caused is 1/14. In a CD system, the longest pulse is even as short as 11T, which means a resolution of 1/11, or a possible error of 1/11. Therefore, the method of utilizing the pulse width to evaluate the frequency is not satisfactorily accurate. Due to the inaccuracy of frequency detection and estimation, when the PLL 100 switches to the PD 110 to lock on the clock signal CLK, the PLL 100 has to spend more time utilizing the PD 110 to lock the clock signal CLK onto the input signal Sin.